Design of approximate multiplier for image processing

Abstract

Today for image processing in smart gadgets, machine learning plays an important role. Low power consumption, fast processing and portability are the essential requirements for designing such smart gadgets. Approximate computing arithmetic circuits are widely employed to satisfy above requirements. In this thesis efficient design and implementation of approximate unsigned number multiplication unit has been presented. Multiplier is widely used to compute different transformation, convolution, etc. Proposed and existing designs are analyzed with respect to area, delay and power consumption. In Digital Signal Processing(DSP) several approaches are made to improve present designs. The modified Dadda Multiplier with different dimensions have been proposed in this thesis, along with their design and analysis, with the goal of reducing output error while applying an accurate compressor. The effectiveness of the modified multipliers is calculated by various experimental assessments of the proposed designs and its parameters are compared with those of the most advanced approximate multipliers. As a result of the findings, it can be seen that the modified multipliers significantly reduce the error rate when compared to the existing approximate multipliers that have been introduced in the literature. The area and the power consumption are both reduced by using the modified multiplier. Furthermore, the latency has been improved in comparison to the existing approximate multiplier. The modified multipliers of 8, 16, and 32 bits are designed and implemented.