Design of a low-power asynchronous 10-bit sar adc in 65 nm technology

Abstract

Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is one of the most popular and widely used ADC architectures due to its high speed, low power, and reasonable resolution capabilities. SAR ADC has gained a lot of interest in recent years because of its suitability for portable and low-power devices. The SAR ADC works by comparing the input voltage to a series of reference voltages generated by a digital-to-analog converter (DAC), and then using a binary search algorithm to determine the closest match. The resolution of the SAR ADC depends on the number of bits in the digital output, and higher resolutions can be achieved by increasing the number of bits. However, increasing the number of bits results in longer conversion times and higher power consumption. Therefore, there is a tradeoff between resolution, speed, and power consumption in SAR ADC design. This thesis focuses on the design and optimization of SAR ADCs, including various circuit topologies, techniques, and architectures to achieve high performance, low power, and high resolution. The research also explores the impact of various process, voltage, and temperature (PVT) variations on the performance of SAR ADCs and proposes techniques to mitigate these effects. Finally, the proposed SAR ADCs are compared with existing state-of-the-art ADCs, and their performances are evaluated in terms of power consumption, speed, and resolution. In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker or neuromorphic applications. Accordingly, the demand for long battery life-time poses the requirement for designing ultra-low power SAR ADCs. Presents work investigates an asynchronous 1.1V 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 65nm CMOS technology. The asynchronous SAR ADC system consists of an internal clock generator, sample and hold switches, capacitive digital-to-analogue converter (DAC), dynamic comparator, and SAR logic. Running a 64-point FFT on the output of the SAR ADC with a 1.2 V differential input signal results in a maximum ENOB of 9.38 bits at 20 MHz sample rate, an SNR of 56.56 dB and aof total power consumption of 676 uW. This SAR ADC system can be used in systems where low power consumption, moderate resolution and moderate speed are mainly required, such as computer memory cores for artificial intelligence applications and sensors for applications, Biomedical and neuromorphic chips.