Accelerating deep network-based image analysis using re-configurable architecture

Abstract

This thesis investigates the utilization of reconfigurable architectures, specifically field-programmable gate arrays (FPGAs), for accelerating deep neural network-based image classification tasks. Four different DNN classification model architectures are analyzed using a custom medical image dataset. The trained model weights are compiled into an hardware-specific model weights and executed on an FPGA board, taking advantage of the parallel processing capabilities and hardware acceleration offered by the DPU architecture. The evaluation of performance and efficiency gains encompasses factors such as inference time, accuracy, and resource utilization. The experimental results demonstrate that the integration of software and hardware components leads to significant improvements in speed and energy efficiency. However, certain limitations and areas for improvement are identified, highlighting future research opportunities for optimizing reconfigurable architectures for image analysis tasks. In summary, this thesis presents a comprehensive exploration of the advantages and challenges associated with reconfigurable architectures for accelerating deep neural network-based image analysis. The findings provide valuable insights into the potential of FPGAs and DPUs in enhancing the performance of image analysis tasks based on deep neural networks and establish a foundation for future advancements in this field.