Some studies on efficient fir filter design using radix-2 booth’s algorithm

Abstract

Booth’s multiplier is known for its versatility due to the signed bit multiplication. For the design of Finite Impulse Response (FIR) Filters, it plays a central role in increasing speed and reducing the power consumption. The work presented in this Thesis is employing Radix-2 Booth’s algorithm for the design of FIR Filters which is primarily classified into two broad categories. The first category deals with the design of a traditional Type-I FIR Filter which is compared with the existing algorithms like Parks-McClellan (PM) and the Improved Sine Cosine Algorithm (ISCA). It is observed that as compared to the PM and ISCA algorithms, the proposed Booth’s multiplier based design requires zero memory and zero Digital Signal Processing (DSP) blocks which in turn leads to a reduced cost and better hardware utilization of Field Programmable Gate Array (FPGA) board. In second category, two designs of a Parallel 2-FIR Filter and an Area-Efficient 2-FIR Filter are presented. The hardware complexity and power utilization of these two filters are compared among themselves, and also with an existing work designed via Xilinx 14.2 Spartan 3E Starter Board XC3S500E chips. Based on the simulation results, it is observed that the proposed Area-Efficient FIR Filter does not require RAMB16s when compared with Parallel 2-FIR Filter and other existing works available in the literature. The Parallel 2-FIR Filter was designed using the Filter Design and Analysis (FDA) toolbox of MATLAB Platform followed by the generation of VHDL file while the Area-Efficient Filter was designed completely using VHDL.