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http://20.198.91.3:8080/jspui/handle/123456789/8839| Title: | Quantum analytical modeling of ultra-scaled double-gate (DG) MOSFET structure and explore its applications |
| Authors: | Chakrabarti, Tyajodeep |
| Advisors: | Sarkar, Subir kumar |
| Keywords: | MOSFET;threshold voltage;AND gate;Inverter |
| Issue Date: | 2022 |
| Publisher: | Jadavpur University, Kolkata, West Bengal |
| Abstract: | As an ineluctable effect of persistent dimensional scaling of transistors, various short- channel effects have become serious challenge for further miniaturization of device dimensions in semiconductor industry. The scenario becomes more complicated as the 'quantum confinement effects’ emerge as an integral part of device characteristics when the ‘channel length’ is dwindled to deep submicron region. Amongst many other proposed structures in sub-nanometer regime, multiple-gate MOSFET structure have proved to be attractive options because of their inherent immunity to ‘short channel effects’ (SCE), improved subthreshold characteristics and enhanced current driving capability. Likewise, Double gate MOSFET provides enhanced mobility, better Ion/Ioff ratio and improved sub-threshold slope due to volume inversion of charge in the channel. In ‘Double Gate (DG) MOSFET’ structure, the vertical field is modified by incorporating dual materials with different work functions in gate, providing a step in potential profile and resulting in enhancement of performance. In this work, the quantum analytical model of DG MOSFET, based on the self-consistent solution of 1-D Schrodinger equation and 2-D Poisson’s equation, for the ultra-scaled ‘double- gate (DG) MOSFET’ structure is proposed. The quantum mechanical effects have been included in our model to derive the analytical surface potential along the channel and expressions for the electric field. Extensive calculations have been carried out to analyse the quantum mechanical effects on other crucial device performance parameters like: threshold voltage, subthreshold slope, ION/Ioff for which result obtained are 0.25V, 66 mV/decade, 155521381.315996 respectively. The two types of MOSFET transistors are fabricated in virtual fabrication lab that is Silvaco Atlas. The fabricated MOSFETs are p-MOS and n-MOS. In both the MOSFET, the two GATEs are considered, which are normally called as ‘DG-MOSFET’. The GATEs are made of polysilicon. The source and drain are made of silicon with the length of 15nm each. The doping is done with p type material, Boron in these sources and drain. The source and drain concentrations are 1e20 and 1e18 respectively. The channel concentration is 1e15 and the length is considered 30nm. In this unique structure we use the two layers of Silicon-germanium (SiGe) in the top and bottom of the channel, with the doping concentration of 1e17. Silicon-germanium enables faster and more efficient manufacturing of devices using smaller, less noisy circuits. This Silicon-germanium is commonly used in heterojunction bipolar transistor or in CMOS transistor for better performance, which has motivated to use in this new novel structure. All the lengths are optimized to get the best possible result. The best solutions are taken in this structure. Furthermore, a comparative analysis based on the drain current has been presented in this work for the classical as well as for the quantum model. The superiority of this proposed quantum model for the DGMOS structure is verified by the comparison of the results obtained from other device structures. As an application part, the proposed structure is applied and used for Boolean implementation as AND gate and as an Inverter. Thus, universal NAND gate can be obtained. Area scaling is a huge issue in today’s VLSI industry. In normal scenario, to construct AND gate 6 transistors are required, using the proposed structure it is seen that only 1 PMOS structure exhibits the function of AND, thus giving a huge boost to the number of devices per die and hence in the VLSI technology. In the future scope of work, it can be examined whether the problems that is generally faced in deep sub- micron technology such as supply voltage scaling, short channel effects can be limited due to the mentioned advantages of DGMOSFET. |
| URI: | http://20.198.91.3:8080/jspui/handle/123456789/8839 |
| Appears in Collections: | Dissertations |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| M.Tech (Dept.of Electronics and Tele-Communication Engineering) Tyajodeep Chakrabarti.pdf | 1.43 MB | Adobe PDF | View/Open |
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