Investigation of SiC trench gate UMOSFET to reduce its on-resistance

Abstract

The SiC U-shaped trench-gate metal-oxide semiconductor field-effect transistors or UMOSFETs are generally known as a SiC MOSFET with low ON-resistance because of the absence of high channel density and JFET resistances. At high drain voltages, during the device operation the gate oxide of UMOSFET suffers from a high electric field. To overcome the problem, in the structure a 𝑝+ shielding region is added at the bottom of the trench. The 𝑝+shielding region guards the gate oxide. But when 𝑝+ shielding region is added, it increases the total ON-resistance as it is introducing a JFET region composed of the drift region, p-body region, and p+ shielding region. In this thesis, an upgraded SiC UMOSFET structure with an added n-type region in the drift region is discussed to reduce ON-resistance of the device. A n-type region is added in the drift layer for that reason depletion region is decreased as a result, ON-resistance of the modified-UMOS is reduced. Here we have compared the ON-resistance of modified UMOSFET with varying the trench depth and implementing the same with simulations using Sentaurus TCAD.