FPGA based implementation of different input size FFT algorithms

Abstract

Transform (FFT) and its inverse (IFFT) are crucial algorithms. Various types of FFT algorithms exist in Digital Signal Processing; among them, the most basic and widely used method is Cooley-Tukey’s Radix-2 FFT technique, but radix-22 FFT algorithm maintains the basic butterfly structure of the radix-2 technique while having the same multiplicative complexity as the radix-4 approach. Several FFT architectures have already been introduced due to their wide range of applications where real-time data is present, such as medical diagnosis and seismic monitoring, etc. This thesis introduces a radix-22 Single-path Delay Feedback (SDF) pipeline architecture for 64, 128, 256, 512, and 1024-point FFT processors based on a Common Factor Algorithm (CFA). The complexity of the radix-2 butterfly is very low compared to the radix-4 butterfly, but the radix-22 CFA uses less twiddle factor than both radix-2 and radix-4 butterfly. These architectures are implemented in the FPGA platform using the Xilinx Vivado 2019.1 synthesis tool of two different FPGA device families. The synthesis results show that these architectures are enhanced in area, delay and logic power.