FPGA implementation of correlation dependent stochastic circuits

Abstract

Stochastic computing exploits random bit streams, realizing area-efficient hardware for complicated functions such as multiplication and tanh, as compared with more traditional binary approaches. Unlike deterministic computing, stochastic computing does not assume that hardware always produces the same results if given the same inputs. It allows for noise and uncertainty (both in the inputs and in how the hardware operates), and tries to use them creatively. Typically, each bit of an N-bit stochastic number (SN) X is randomly chosen to be 1 with some probability P(X), and X is generated and processed by conventional logic circuits. For instance, a single AND gate performs multiplication. The value X of an SN is measured by the density of 1s in it. SC has uses in massively parallel systems and is very tolerant of soft errors. In this Thesis we have first briefly studied about SC, its generation which includes like random number generation, derandomizer unit, correlation among input values, etc and have subsequently developed stochastic computational elements for certain operations. Finally implemented some of the stochastic circuits in hardware either using circuitmaker and breadboard or FPGA.