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http://20.198.91.3:8080/jspui/handle/123456789/6352Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chatterjee, Sayan , Prof. | - |
| dc.date.accessioned | 2024-07-10T09:45:36Z | - |
| dc.date.available | 2024-07-10T09:45:36Z | - |
| dc.date.issued | 2024-07-10 | - |
| dc.identifier.uri | http://20.198.91.3:8080/jspui/handle/123456789/6352 | - |
| dc.language.iso | en | en_US |
| dc.publisher | Jadavpur University | en_US |
| dc.subject | Basics of VLSI | en_US |
| dc.subject | Tools- Cadence Virtuso | en_US |
| dc.subject | Verilog | en_US |
| dc.subject | VHDL coder | en_US |
| dc.subject | SPICE | en_US |
| dc.title | Selected Lecture Notes on VLSI Design | en_US |
| dc.type | Presentation | en_US |
| dc.department | Electronics & Telecommunication Engineering | en_US |
| Appears in Collections: | Prof. Sayan Chatterjee | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Cadence Virtuoso.pptx | 2.79 MB | Microsoft Powerpoint XML | View/Open | |
| DFM_ug.pptx | 3.66 MB | Microsoft Powerpoint XML | View/Open | |
| JU lecture EDA - UG.pptx | 7.79 MB | Microsoft Powerpoint XML | View/Open | |
| SPICE modelling_ug.pptx | 3.98 MB | Microsoft Powerpoint XML | View/Open | |
| Verilog.pptx | 3.31 MB | Microsoft Powerpoint XML | View/Open | |
| VHDL- AMS.pptx | 1.13 MB | Microsoft Powerpoint XML | View/Open | |
| VHDL_class_JU-1-UG.ppt | 2.17 MB | Microsoft Powerpoint | View/Open | |
| VHDL_class_JU-2_UG.ppt | 2.08 MB | Microsoft Powerpoint | View/Open |
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