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Please use this identifier to cite or link to this item: http://20.198.91.3:8080/jspui/handle/123456789/2712
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DC FieldValueLanguage
dc.contributor.advisorDas, Debesh Kumar-
dc.contributor.authorPal, Debasis-
dc.date.accessioned2023-06-09T07:38:08Z-
dc.date.available2023-06-09T07:38:08Z-
dc.date.issued2016-
dc.date.submitted2016-
dc.identifier.otherDC3169-
dc.identifier.urihttp://20.198.91.3:8080/jspui/handle/123456789/2712-
dc.format.extentix , 57p.en_US
dc.language.isoenen_US
dc.publisherJadavpur University, Kolkata, West Bengalen_US
dc.subjectVLSI circuiten_US
dc.subjectNano scale VLSI circuitsen_US
dc.subjectDouble Patterning Lithography (DPL)en_US
dc.subjectTriple Patterning Lithography (TPL)en_US
dc.subjectresolution enhancement technique (RET)en_US
dc.titleA new approach in design for manufacturing for nanoscale VLSI circuitsen_US
dc.typeTexten_US
dc.departmentJadavpur University. Computer Science & Engineeringen_US
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