Design of multi-channel frequency hopping spread spectrum transceiver for wireless communication

Abstract

Abstract Despite the fact that spread spectrum communication technique was originally used by military for interference rejection and enciphering, use of spread spectrum for jamming resistance became a popular concept by the end of World War-II. Further investigation of spread spectrum motivated by the need of highly jamming resistant communication systems, resulted in many other applications like energy density reduction, high resolution ranging and multiple access etc. Recently, spread spectrum techniques have found their way into many other consumer and industrial applications such as PCS phones, cordless telephones, wireless card readers, bar code scanners, blue tooth communication and so on. The overall system performance of any spread spectrum communication system is directly a ected by the speed and reliability of the spread spectrum transceiver and hence demands for high transmission rate, high quality and security necessitate high speed and at the same time high performance spread spectrum transceivers. This thesis is speci cally focused on the design and analysis of frequency hopping spread spectrum transceiver for wireless communication applications with particular attention to transmitter and receiver system design. This work also attempts to address the issues associated with the design of some of the critical CMOS RF analog circuits employed in the proposed architecture. The key analog circuit block in the transmitter is the Voltage Controlled Oscillator (VCO) with reasonably wide bandwidth. We have designed a new CMOS current starved voltage controlled ring oscillator (CSVCRO) and veri ed it by simulating in CMOS technology. The VCO architecture proposed here provides high linear relationship between oscillation frequency ranging from 0:7-1:75GHz over a control voltage ranging from 1:2-2V and results in a large tuning range of 75%. The phase noise achieved is -88dBc/Hz at an o set frequency of 1MHz. The linear frequency sweep is obtained without employing any additional compensation techniques resulting in less circuit complexity, die area and power consumption. We have also custom-designed the digital and mixed signal circuits such as 4-bit data word generator, PN sequence generator, 8:1 multiplexer, serial-to-parallel (S2P) converter, Digital-to-analog converter (DAC)etc. using the standard architectures in order to complete the transmitter system. The key analog circuit blocks in the receiver section are the RF front-ends such as Low noise ampli er (LNA), wide band or frequency independent precision recti er and the Frequency-to-voltage converter (FVC). We have designed a CMOS based low noise ampli er with L-type input matching network and -type output matching network. The input L-type matching network is used to x the Q-factor whereas the output - type matching network provides an extra degree of freedom to adjust the bandwidth. Simulation results reveal that a gain of 22:7 dB for the frequency range of 0:9 to 6GHz and noise gure (NF) of 2:5 dB are obtained and are reasonably good in comparison to the reported works. We have also conceptualized a new sinusoidal full wave precision recti er architecture which was implemented with discrete components and validated by experimentation. The circuit gives a d.c. output voltage, the magnitude of which is nearly the same as the peak input voltage over a frequency range of 50Hz to 1MHz with a very low ripple voltage and low harmonic distortion. The architecture was modi ed in order to remove the frequency dependency that arises at the present high frequency application and was implemented using CMOS technology. Simulation results reveal that the circuit recti es small (mV) a.c. signals at 1GHz and a little beyond. We have also designed and implemented the sub-circuits like analog-to-digital converter (ADC), parallel-to-serial converter (P2S), Di erentiator, Integrator, Logarithmic and anti-logarithmic ampli ers, Comparator, Coding network etc. using standard topologies in order to complete the receiver system. The successful design of the individual RF blocks (analog, digital and mixed signal) and their simulation results demonstrate that it is feasible to achieve a fully integrated frequency hopping spread spectrum transceiver architecture as proposed in this thesis without employing PLL, FLL or DDFS for frequency synthesizing with reasonably good noise performance.