Performance improvement for future NANO devices and explore some of their applications

Abstract

ABSTRACT Continuous demand for performance improvement of the device haves shepherd semiconductor industry to miniaturization of the MOS device. After more than forty decades of scaling of the device it comes to its limitation. To continue the process of scaling urgent innovation for new and innovative device structure with new material for MOS is required. Short channel effect is the main hinder for further scaling of bulk MOSFET. Development of crystal growth technique has provide Silicon-on-Insulator (SOI) MOSFET to semiconductor technology. It is a new innovative device which use buried oxide layer in between the channel and the substrate to overcome the different type of parasitic capacitance effect. The use of double gate and then enhance by dual metal double gate allow to reduce the size of the device to thin level. Dual metal double gate use the concept of gate engineered to have a precise control of gate over the channel. The performance of the device is further enhance by using air as a buried layer which will reduce the capacitance of the buried layer and make it more efficient in terms of speed, size and power consumption. The new device is Silicon-on-Nothing (SON) MOSFET. The implementation of work function engineered DMDG SON MOSFET transform the size of the device to level of ultra thin dimension. The ultra thin device dimension will generate some critical issues for the recent semiconductor device, such as increase of source drain region, quantization of carrier and gate oxide breakdown. A proper analysis and modeling of device is required with reference to the above critical issues to provide a better performance in terms of low threshold voltage, drain current, further scaling and its application to VLSI circuit. This thesis work incorporate different novel DMDG SON device structure with analytical modeling for potential profile, threshold voltage and drain current considering the increase of source/drain resistance, quantization of carrier and gate oxide breakdown for performance improvement of nano device. In order to meet the future demand for nano device, researcher has to look beyond CMOS. Single Electron Transistor (SET) is such a device which can control the flow of single electron. MOS the most regularly use present semiconductor device is complementary to SET. So use of the hybrid SET-MOS circuit utilizing the benefit of both SET and MOS will be one of the future generation nano circuit. So the thesis also consist an application of hybrid SET-SOIMOS circuit.