IEEE 754 floating point number representation and division using 8-bit register

Abstract

This paper presents an overview of the IEEE 754 standard for floating point number representation and a detailed method for performing division operations using the Restoring Division Algorithm with four 8-bit registers. IEEE 754 is the established standard for floating point arithmetic in computer systems, defining formats and operations to ensure consistent and accurate computational results across different platforms. The standard includes various precision formats such as single precision (32-bit) and double precision (64-bit). The focus of this study is on implementing floating point division within resourceconstrained environments, specifically using four 8-bit registers to store and manipulate data. This involves dissecting the IEEE 754 floating point representation into its three key components: sign, exponent, and mantissa. The Restoring Division Algorithm, a classical method for binary division, is employed to perform the division of mantissas. The proposed method outlines the step-by-step procedure of normalizing the operands, aligning the exponents, and executing the Restoring Division Algorithm on the mantissas. This is followed by adjusting the resulting exponent and reassembling the final floating point result. Special cases such as division by zero, overflow, and underflow are carefully considered and handled to maintain compliance with the IEEE 754 standard. This implementation addresses the challenges of maintaining precision and accuracy within the constraints of limited register size. The approach demonstrates how efficient floating point division can be achieved using minimal hardware resources, which is particularly relevant for embedded systems and other low-power devices. The results show that it is possible to perform IEEE 754 compliant floating point division using the Restoring Division Algorithm with four 8-bit registers, providing a practical and efficient solution for computationally constrained environments. This work contributes to the field of embedded system design by offering a viable method for implementing floating point arithmetic, balancing computational efficiency and precision within the limitations of small-scale hardware.