Nanodevices and their application in circuits with emphasis on circuit reliability and stability

Abstract

The ever increasing demand of miniaturization to support the advancement of the technological progress seeks attention towards the devices beyond the MOS technology as it is equipped with the different short channel effects in the sub-nanometer regime. Among the different nanodevices the Single Electron Device (SED) is being studied extensively by the researchers to utilize its unique features for replacing the conventional MOS completely or partially. Research work in this domain is mainly carried out by fabrication, characterization of the different SEDs and the circuit design aspect of the technology. The fabrication of the device is an expensive as well as a very time consuming affair. The circuit design area of Single electron Technology demands the equivalent models along with the simulation software platforms for testing. The aim behind doing so is the reduction of time constraints and predicting the circuit behavior under different parameter variations but in a cost effective way. The simulation of the Single electron Transistor (SET) based circuit implementation necessitates equivalent model of the practical SET. Here in this thesis the structure and development of the Macro Model to support practical SET functionalities is portrayed with necessary simulation results and comparisons with previously proposed models. The model is established by designing two SET based benchmark circuits such as inverter and the Multi-peak negative-differential-resistor. The linearization of the input output relationship for a particular device is often required to properly characterize the designed circuits in presence of small-signal. The SET lacks of the development of any small-signal model. The investigation of the frequency dependence of associated intrinsic and extrinsic parameters is carried out. The effects of the parasitic components on the device small-signal parameters are also evaluated. The circuit design side of SED includes the details of the circuits constructed by the Threshold Logic Gates (TLGs) implemented with Single Electron Tunneling Technology (SE-TLG). The five input majority gate circuit and the function implementation using Programmable Logic Array is presented with SE-TLG approach. Both the circuits are simulated with the widely accepted SED simulator SIMON. The computation of the related power dissipation and delay is elaborated. These circuits facilitate with extremely low power consumption in the range of pico-Watts and nano-scale size. The partial replacement of the MOS in CMOS technology accommodates the strengths of MOS and SET both. The co-simulation of SET-CMOS based circuit is done with Tanner SPICE by using SPICE compatible equivalent model of both. Two circuits namely half subtractor and a two-bit binary multiplier are implemented with this hybrid approach and the simulated results, power consumption are furnished. Moreover a comparative analysis has been demonstrated between the conventional CMOS, SE-TLG and SET-CMOS based comparator implementation. While designing a circuit with any technology the performance of that particular circuit is evaluated with the analysis of circuit reliability and stability. The reliability of a circuit is a severe issue to be taken care of as unreliable operation of a circuit leads to the erroneous output. For the SEDs the background charge results in circuit malfunction. The randomly distributed charges are taken into account for reliability determination of the designed SE-TLG based PLA circuit. The effect of the island shape and size on reliability of the same circuit is also investigated. Another method of reliability analysis is also deliberated for a SE-TLG combinational circuit using combined MC and Probability Transfer Matrix. The results of the combined method have been compared with the results of purely MC based method of reliability assessment. The stable operation of a SED indicates no tunneling of electrons which implies zero tunneling current or the Coulomb Blockade state, provided the temperature is 0K and co-tunneling is absent. The circuit stability of the SE-TLG based PLA and an inverter circuit is studied with varied input combinations. The parametric variation effects on the circuit stability is also studied. Finally the stability analysis of the hybrid SET-CMOS based inverter circuit is elaborated. As a whole the thesis familiarizes with the development of Macro model and small-signal model of SET, circuit design and testing of several important circuits with SE-TLG as well as SET-CMOS approach. The designed circuit performance is also examined with the corresponding reliability and stability analysis.