Study and design of emerging nanoscale mosfets

Abstract

Conventional MOSFET structures are reaching scaling limits and Short-Channel Effects (SCEs) have become most important issue for device performance. With the reduction in feature size, the density of the transistors as well as the performance in terms of speed increases, leading towards the concept of System-on-Chip (SoC) which integrates all the elements of a system (Digital, analog and RF) within the single chip. High frequency performance and power consumption of the circuits is also largely affected due to SCEs. At the nano-dimensional scale, the influence of SCEs on the characteristics of conventional MOSFETs cannot be ignored. In current work, the problems associated with the emerging nanoscale MOSFET devices are studied and reported. In first part, the Silicon Junctionless FinFET has been considered and its analog/RF performance is analyzed. In the second part the Analog, RF and Linearity performance of InGaAs/InP hetero-junction MOSFET is studied. Using extensive 3D TCAD simulations of n-channel Junctionless Accumulation Mode bulk FinFET, it is demonstrated that the high-k spacers improve the electrostatic integrity of FETs with sub 20 nm gate lengths. It is observed that the digital and analog performance of the device improves with high-k gate spacers. However, using high-k spacer material, the device performance is not good for RF applications. Simulation results also suggest that RF/analog performance of the device with spacer having high-k dielectric can be improved by reducing the spacer length. Effect of Fin width variation and shape of the Fin cross-sectional shape is also evaluated for the RF/analog performance of the device. It is concluded that reduction of Fin width can cause improvement in device performance in order to find their usage in analog as well as RF applications. From the analysis of Fin cross-sectional shape, an optimized value of Fin top width and Fin shape is suggested. This design is expected to provide better SCEs and reasonable maximum oscillation frequency to use the device in RF/Analog applications. Analog, RF and Linearity performance of InGaAs/InP hetero-junction MOSFET using TCAD device simulation is also carried out. A detailed investigation of the impact of InP barrier layer thickness is reported. It is found that the RF and Analog performance of the device improves as barrier layer thickness reduces. It is understood that a trade-off is required depending upon the device application area. The impact of the channel doping and channel composition on the vital performance of the InGaAs/InP heterostructure DG MOSFET is also examined. It is found that, a trade-off in channel composition must be made to optimize the device performance and device reliability. This research for emerging nanoscale devices such as Junctionless Accumulation Mode bulk FinFET and heterostructure MOSFET, through intensive TCAD simulations, suggests the optimal device parameters and structures. Therefore, it is established that understanding of device physics insight with design of new structures and material compositions are very crucial for enhancement of next generation device performances.