Exploring the novel characteristics of hetero-material gate field effect transistors

Abstract

In the present era of human civilization, electronic components have become indispensible in every sphere of life from industrial process control, automation to consumer electronics/wireless communication. In the last few decades, this excessive dependence on process automation and people’s desire for lavish lifestyle, increased safety, security and high speed real-time interconnectivity have been propelling the technology boon in industrial automation and state of the art consumer electronics. This rapid growth in the field of electronics has been accompanied by constant device miniaturization in accordance to Moore’s law. Reduction of circuit dimension reduces the overall circuit area, allowing more devices on a single die increasing circuit speed, integration density and reducing the cost and power without negatively impacting the cost of manufacturing. Ever increasing trend of device dimension down-scaling to deep sub-nanometer range allows the researchers to explore complex integrated systems on a single chip which drastically reduce their volume and power consumption per function, thereby resulting in a tremendous increase in the speed of operation and increases functionality of electronic devices. However, this fanatic pace of device dimension down scaling cannot continue indefinitely. A series of daunting challenges crop up in the areas of device fabrication combined with some inevitable performance degrading short channel effects which limit further miniaturization of CMOS devices unless these practical challenges are taken care of. Researchers have been working persistently to come up with some innovative non-conventional device structures as possible solutions to the challenges associated with sub-nano device operations. Silicon-on-Insulator (SOI) MOSFET can efficiently replace age old bulk MOSFET by exhibiting superior performance expected from next generation Si technology. Introduction of a buried oxide layer under the channel layer in a SOI structure reduces parasitic capacitances, thereby mitigating several performance deteriorating factors while simultaneously reducing propagation delay ensuring SOI to be a faster device. Moving one step further, the buried oxide of simple SOI structure can be replaced with air having a lower dielectric permittivity than oxide realizing a new Silicon-on-Nothing (SON) structure. SON is practically an improvised version of basic SOI capable of exhibiting momentous improvement in device operating speed and performance by further reducing the capacitive effects of parasitic junctions. Moreover, strain may also be incorporated in the channel region of a conventional MOS structure to enhance carrier mobility and realize notable increase in current drive and operating speed. Apart from the SOI/SON technologies, another research avenue is to realize ‘multiple’ gate MOSFETs exhibiting better control of gate electrode over the conducting channel capable of enhancing current drivability, mitigating SCEs, improving sub-threshold slope, thus ensuring better scalability. Gate material engineering can be also considered as an emerging research area where the vertical gate electric field and subsequently the overall electric field in the channel region of nano scale devices can be adjusted by placing two or more metals with dissimilar work functions adjacently as a single gate electrode and the potential profile shows a sudden step due to work function disparity which is particularly effective to mollify Drain Induced Barrier Lowering (DIBL) related issues. The concept of gate material engineering can be extended to a further extent by considering binary metal alloy as gate electrode material where the individual work functions of the constituent metals are continuously varied spatially so that the gate electrode has different values of effective work function at different positions along channel direction. This unique feature of spatially varied work function reduces surface potential profile asymmetry in short channel devices, thereby improving the performance due to DIBL attenuation. Moreover, the most critical issue of precisely sharp source/drain junction formation in every nano dimensional junction based devices can be dealt with by employing Junctionless (JL) devices where the type and concentration of source and drain doping are essentially same as that in the channel region, thereby eliminating the formation of any junction, and consequently annihilating impurity dopant diffusion associated with severe concentration gradient across the junction. In spite of a number of endeavours to develop innovative MOSFETs, one of the basic drawback of MOS technology is the limiting value of subthreshold slope achievable impeding the use of MOSFETs in applications where power consumption is a crucial issue. The principle of carrier tunnelling enables Tunneling Field Effect Transistor (TFET) to overcome MOSFET’s thermal limit of 60 mV/dec and to achieve much reduced value of subthreshold slope. Thus, TFET can be regarded as a potential candidate for next generation ultra low power, ultra low voltage applications. Developing an accurate analytical model is mandatory for gaining in depth knowledge about the operation of these newly emerging devices. In view of this, the thesis presents a comprehensive analytical study of the improved characteristics of several hetero-material gate Field Effect Transistors by embodying the extreme exploration of the pioneering concept of gate material engineering. The analytical results obtained from different proposed device structures studied throughout this dissertation are compared with relevant simulation results to establish the supremacy of these devices as possible alternatives for future semiconductor industry.