Performance improvement of low dimensional devices and explore some of their applications

Abstract

Microelectronics devices with low power have got tremendous importance in our modern lives. Low dimensional devices deals with the performance improvement & miniaturization of ICs. The evolution of miniaturization has produced complex system-on-chip (Soc) in which millions of transistor packed on a single silicon chip through the use of CMOS based ULSI technology platform. This has led to CMOS technology towards the deep sub-50 nm regime. However further miniaturization of MOS Transistors are facing GIDL limit and several unwanted problems like short channel effects (SCEs),Hot carrier effects, Gate-Dielectric reliability etc. arises. Due to the short channel Source/Drain encroachment begins to limit the gate‟s ability to control the channel and this causes Drain induced barrier lowering (DIBL) effect and threshold voltage roll–off problems. Also the leakage current of a scaled down transistor through the PN junction between the Si Substrate and the Source/Drain region increases which prevents the use of scaled down transistor in low standby power application. Moreover, the parasitic capacitances of transistor may strongly affect the characteristics of CMOS devices. Therefore, the use of planner technology for ULSI circuit becomes more challenging. This has led to researchers to investigate the device technology in two ways- one is SOI-MOSFET, SON-MOSFET, DMDG SON, DMTG SON etc. which are basically Extended CMOS type and another is beyond CMOS devices like SET, spintronics, straintronics etc. Recently SOI technology has demonstrated promise for nano-CMOS scaling. In SOI a buried oxide layer (BOX) is placed under the Si active layer. This BOX can be seen as a blocking layer to reduce the fringing field effect (Drain Induced electric field) which reduces the lower off state leakage current and parasitic capacitances. SON MOSFET is achieved by replacing BOX layer with unity dielectric, i.e.air. The main advantages of SON MOSFET are their radiation immunity in extreme environment, less power consumption, further downscaling capability, low noise, higher short channel immunity, reduced fringing field effect and faster switching action due to lowest parasitic capacitance and low cost. Higher insulation of channel from thesubstrate with lowest dielectric constant material „air‟ at box region, makes it suitable as a device at extreme climatic condition. In a SON structure thresholds voltage is also much resistive against different SCEs as a result it shows lower threshold voltage roll off and less sub-threshold slope then SOI structure. Dual-material double gate (DMDG) structures have been developed as a part of multi material gate engineering. In this technology gate electrode consist of either two metals or metal like materials placed in a symmetric manner or a binary metal alloy (AxB1-x ) having linearly graded work functions. The material with higher work function is placed at the source side to get better result. Now DMDG and Dual material tri-gate coupled with SON MOSFET shows a dramatic improvement over short channel effect than its counterpart which is examined in this thesis. Among the beyond CMOS devices spintronics based research has become very prominent in the recent times. This makes candidate a venture in the area of spintronics where digital circuits have been designed and explored the feasibility of some real life application using single spin logic circuits like spintronics based RFID system which is ultra-dense, low power consuming and can be used in high speed VLSI/ULSI integrated circuits which is discussed in this thesis. In straintronics the effect of stress on the magnetic energy of the device, via the magnetostriction property of the free layer is introduced which consumes much less energy and hence is more suitable for Nanomagnetic logic. Nanomagnetic logic can encode the logic bits through their bistable magnetization orientation. So, this logic system can be simultaneously used to process the binary information as well as basic memory building block. Here, the possibilities of designing two basic universal gates are discussed with ultra low power dissipation which can easily be operated from the energy harvesting from the nature. Straintronics with the combination of MTJ makes the device more ubiquitous, so that input and output parameters can easily be penetrated. This Thesis examines the concept of straintronics switching and the intrinsic magnetic energies of the free layer of the MTJ and to design a three input NOR gate based on the model of the straintronics MTJ combination with a very high figure of merit.